影片說明
#RISCV #RV32I #instructionformat
Course material: https://tinyurl.com/ca-renzym
Images taken from this book (also links to his own lectures on this page): https://github.com/johnwinans/rvalp
Topics Covered:
(00:00) Review and why RISCV
(09:26) Skippable - Motivation
(19:40) RISCV Reg-Reg ALU instruction format
(22:31) RISCV ALU immediate instruction formats
(26:05) RISCV Load instruction (LW/LB/LH) format
(28:56) RISCV Store instruction (SW/SB/SH) format
(29:42) RISCV Branch instructions format
(32:22) RISCV JAL/JALR instruction format
(36:32) RISCV LUI/AUIPC instruction and format
(45:13) RISCV Instruction formats, putting it together
(49:27) RISC processor Control logic design
(1:02:17) Iron law of processor performance
(1:11:53) What determines cycle time and pipeline intro
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